The subject matter disclosed herein relates to solutions for solving integrated circuit layout optimization. Specifically, aspects of the invention relate to a parallel solving approach to layout optimization.
In large-scale integrated circuit layout design, layout migration and design for manufacturability (DFM) optimization are conventionally employed. In many cases, long run-time becomes an issue in solving layout migration and DFM optimization in these large-scale layouts. Specifically, the linear programming (LP) process associated with layout migration and DFM optimization can be time consuming.